Physical Design Challenges in FinFET Technology

Abstract

Fin Field-Effect Transistor (FinFET) is another major development in semiconductor device scaling as it provides better solutions for short-channel effects of FinFETs, low leakage currents, and high drive currents. These advantages make FinFET a leading choice for the manufacturing of High Performance and Low Power Integrated Circuits. However, the fact that FinFETs have a three-dimensional structure creates several physical design issues that must be mitigated to knock out the true advantage of the new structure. The remaining part of this paper delves deeper into these challenges with emphasis on layout, performance, power and energy consumption, variability and manufacturing issues. The relation between FinFET geometry and layout design is presented, and it is more complex than that of planar transistors and affects layout parasitic capacitance and resistance. Important and special attention is paid to the correct and appropriate modeling and simulation techniques required, which help in predicting the behavior of the device and assist the designer in solving the problem. The kind of lithography required for manufacturing FinFETs is discussed together with the plan to raise the yield and reduce variability. This paper systematically surveys the literature and various advancements in FinFET design: new methods and tools. This section explains the methods used in the experimentation such as simulation tools and optimization methods of FinFET designs. While results and discussion sections contain empirical data and self-explanatory case studies, the trade-off between performance, power, and variability in FinFET design is thoroughly covered. This paper ends by presenting major conclusions and possible studies for improving the physical design and manufacturability of FinFET technology.